ML on Edge Hardware
Electron/Photon Classification BDT on FPGA
University of Zurich · CMS / CERN · 2019 – 2024
Designed the first machine-learning algorithm to run in the CMS Phase-2 hardware trigger: an electron/photon classification boosted decision tree implemented in FPGA firmware at 100 ns latency, using under 3.1% of chip logic, raising selection efficiency by up to 10%. Recognised with a CMS Award (2023).
A first for the experiment
When the CMS trigger is upgraded for the high-luminosity LHC, its earliest, fastest selection stage runs entirely in FPGA firmware. Historically that stage used hand-tuned cuts. I designed the first machine-learning algorithm ever slated to run there: a boosted decision tree that classifies electron/photon candidates.
The engineering constraint is severe. The model must return an answer in 100 nanoseconds and share the chip with everything else the trigger does — so it had a budget of under 3.1% of the FPGA logic resources.
Model and firmware
I trained the BDT with XGBoost and translated it to firmware with conifer/HLS, tuning tree depth and count against the latency and resource budget. The deployed model raised the selection efficiency ε(pT) by up to 10% relative to the cut-based baseline — real physics reach, delivered within a fixed hardware envelope.
The work received a CMS Award in 2023 for its contribution to the Phase-2 L1T e/γ algorithm and its firmware implementation.
